Search

Chisel: A Modern Hardware Design Language

A fast TCP/UDP tunnel over HTTP

Digital Design with Chisel

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel.

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Chisel RISC-V Vector 1.0 Implementation