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Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

Sail RISC-V model

RISC-V Instruction Set Manual

A Linux-capable RISC-V multicore for and by the world

Open-source library of optimized deep learning operations (matmul, convolution, attention) for CPUs (x64, AArch64, RISC-V) and Intel GPUs. Used by PyTorch, TensorFlow, OpenVINO, and ONNX Runtime.

Modern co-simulation framework for RISC-V CPUs

The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.

This tool lets you search your gadgets on your binaries to facilitate your ROP exploitation. ROPgadget supports ELF, PE and Mach-O format on x86, x64, ARM, ARM64, PowerPC, SPARC, MIPS, RISC-V 64, and RISC-V Compressed architectures.

Spike, a RISC-V ISA Simulator

RISC-V Opcodes

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

GNU toolchain for RISC-V, including GCC

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

PicoRV32 - A Size-Optimized RISC-V CPU

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A RISC-V ELF psABI Document

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

OpenEmbedded/Yocto layer for RISC-V Architecture

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

CKB's vm, based on open source RISC-V ISA

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

RISC-V Packed SIMD Extension

Xv6 for RISC-V

Text describing xv6 on RISC-V

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel.

Super fast RISC-V ISA emulator for XiangShan processor

Open-source high-performance RISC-V processor

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

Patches & Script for AOSP to run on Xuantie RISC-V CPU