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Verilator open-source SystemVerilog simulator and lint system

VUnit is a unit testing framework for VHDL/SystemVerilog

Verilog/SystemVerilog support for VS Code

SystemVerilog to Verilog conversion

SystemVerilog parser library fully compliant with IEEE 1800-2017

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Compact 80386 CPU in SystemVerilog

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.