chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++477 stars91 forksApache-2.0

antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard

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chipsalliance/Surelog has 477 GitHub stars. It gained 0 stars over 1 recorded day in the last 7 days and 0 over 4 recorded days in the last 30 days (snapshots through Nov 6, 2026).

It currently ranks #19786 daily, #20568 weekly, #9234 monthly by momentum on Trending Repos; its best-ever rank is #1440.

Trending Repos first recorded it on May 22, 2026.

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PeriodRankScore

Daily

#197860.0

Weekly

#205680.0

Monthly

#92340.1

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Best rank #1440

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Date	Stars gained	Total stars	Forks gained
Nov 3, 2026	0	476	0
Oct 27, 2026	0	476	0
Oct 18, 2026	0	476	0
Oct 9, 2026	0	475	0

chipsalliance/Surelog

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chipsalliance/Surelog

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