VHDL compiler and simulator
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8 results for “vhdl”
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VUnit is a unit testing framework for VHDL/SystemVerilog
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UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
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A huge VHDL library for FPGA and digital ASIC development
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A fast VHDL language server and analysis library written in Rust
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A tiny Open POWER ISA softcore written in VHDL 2008
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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
7 daysStars17024h gain-Score0.0