Verilog

Docs, design, firmware, and software for the Haasoscope

一步一步写MIPS CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A tiny Open POWER ISA softcore written in VHDL 2008

iCESugar FPGA Board (base on iCE40UP5k)

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

RISC-V Formal Verification Framework

Verilog HDL files

Opensource DDR3 Controller

Amiga Minimig ported to the Tang Nano 20k FPGA

Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

A Verilog implementation of Fast Polynomial Multiplier (FPM) using Number Theoretic Transform.

Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second.

An open-source AI accelerator, developed by AI: RTL, ISA, simulator, compiler and profiler in one repo. Runs Qwen3, LFM2.5 and Qwen3.5 on a Kintex-7 PCIe card.