dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl

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dpretet/async_fifo has 491 GitHub stars.

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